
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:38:40 05/25/2015
// Design Name:   cpu_top
// Module Name:   E:/File/ISEProject/PipelineCpu/testbench.v
// Project Name:  PipelineCpu
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: cpu_top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

// instruction 
`define NOP	5'b00000
`define HALT	5'b00001
`define LOAD	5'b00010
`define STORE	5'b00011
`define SLL	5'b00100
`define SLA	5'b00101
`define SRL	5'b00110
`define SRA	5'b00111
`define ADD	5'b01000
`define ADDI	5'b01001
`define SUB	5'b01010
`define SUBI	5'b01011
`define CMP	5'b01100
`define AND	5'b01101
`define OR	5'b01110
`define XOR	5'b01111
`define LDIH	5'b10000
`define ADDC	5'b10001
`define SUBC	5'b10010
`define JUMP	5'b11000
`define JMPR	5'b11001
`define BZ	5'b11010
`define BNZ	5'b11011
`define BN	5'b11100
`define BNN	5'b11101
`define BC	5'b11110
`define BNC	5'b11111
//register
`define gr0	3'b000
`define gr1 3'b001
`define gr2 3'b010
`define gr3 3'b011
`define gr4 3'b100
`define gr5 3'b101
`define gr6 3'b110
`define gr7 3'b111



module testbench;

	// Inputs
	reg clock;
	reg reset;
	reg start;
	reg enable;

	// Outputs
	wire [15:0] d_dataout;
	wire [7:0] d_addr;
	wire [7:0] i_addr;
	wire d_we;
	wire [15:0] reg_A,reg_B;
	wire [15:0] id_ir,ex_ir,mem_ir,wb_ir;

	// Instantiate the Unit Under Test (UUT)
	pcpu uut (
		.clock(clock), 
		.reset(reset), 
		.start(start), 
		.enable(enable), 
		.d_dataout(d_dataout), 
		.d_addr(d_addr), 
		.i_addr(i_addr), 
		.reg_A(reg_A),
		.reg_B(reg_B),
		.id_ir(id_ir),
		.ex_ir(ex_ir),
		.mem_ir(mem_ir),
		.wb_ir(wb_ir),
		.d_we(d_we)
	);
	
	always #5 clock = ~clock;
	integer x;	
	initial begin	
		x = 0;
		clock = 0;
		reset = 0;
		start = 0;
		enable = 1;
		
/*	   $display("pc id_ir: regA regB cf ALUo:  regC da dd   w: reC1:   gr0  gr1  gr2  gr3  gr4  gr5  gr6  gr7");	  
		$monitor("%h %h:  %h %h %b %h:  %h %h %h %h:  %h:  %h %h %h %h %h %h %h %h",
			     uut.pc, id_ir,reg_A,reg_B,uut.cf, uut.ALUo, uut.reg_C,d_addr,d_dataout, d_we,uut.reg_C1,uut.gr[0], uut.gr[1],uut.gr[2],uut.gr[3],uut.gr[4],uut.gr[5],uut.gr[6],uut.gr[7]);
*/	  
  	   enable <= 0; start <=0; reset <=0; 
      #10 reset <= 0;
      #10 reset <= 1;
      #10 enable <= 1;
      #10 start <= 1; 
      #10 start <= 0;
		#20000
		repeat(256)
		begin
			$display("Add: %x, Cell: %x",x,uut.d_mem.d_mem[x]);
			x = x+1;
		end 
		$finish;
	end
 
endmodule
